The present invention pertains to methods for forming a seed layer on an integrated circuit. More specifically, the methods include at least two operations. The first operation deposits seed material via PVD to provide some coverage, minimizing formation of overhang at feature openings. The second operation redistributes a portion of the seed material deposited in the first operation onto the sidewalls of the features, while simultaneously depositing additional material at least to the upper sidewalls.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer. (inter-metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching. In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below.
Presented in FIGS. 1A-1H, is a cross sectional depiction of a dual Damascene fabrication process. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which; a diffusion barrier 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive materials have high diffusivities and readily diffuse into the ILD, the underlying silicon devices must be protected from metal ions (e.g., copper) that might otherwise diffuse into the silicon. Suitable materials for diffusion barrier 105 include tantalum, tantalum nitride, titanium nitride, and the like. In a typical process, barrier 105 is formed by a physical vapor deposition (PVD) process such as sputtering or a chemical vapor deposition (CVD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in damascene processes, as depicted in these figures. After fill of metal layer 107 (above the field) the excess metal is removed to the field level (as well as portions of diffusion barrier 105 on the field). This leaves metal inlay 107 exposed on the field region for construction of additional layers. The resultant partially fabricated integrated circuit 100 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1H.
As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.
The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.
Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a conformal diffusion barrier 123. As mentioned above, barrier 123 is made of tantalum, tantalum nitride, titanium nitride, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electroplating of the features with copper inlay. It is desirable to deposit a uniform conformal layer, but a major problem with conventional PVD methods of depositing seed layers is formation of xe2x80x9coverhangxe2x80x9d around the openings (top-most portions) of device features. See FIG. 1G. Commonly, a high RF-bias sputter is used to deposit a metal (e.g. copper) seed layer, 124, on diffusion barrier 123. For example, Gopalraja et al. (U.S. Pat. No. 6,724,008) describe a method of via filling including a first step that uses a highly-ionized copper plasma with an RF bias applied to the wafer platen, followed by a more neutral deposition. Using such methods, generally more material is deposited onto the device feature surfaces at the top of the features than at the bottom. This is especially true with high aspect ratio ( greater than 3:1) features. Due to re-sputter of more heavily deposited material on the field, overhang, 126, is formed at the aperture of trenches 121. This overhang is problematic because in subsequent metal fill (e.g. electroplate), the overhang prevents complete fill of the features. This creates voids in the metal inlay that causes at best device unreliability or at worst unusable devices. As well, in the high-power low-pressure sputter first step, the wafer incurs a heavy heat load. This is particularly undesirable for low-k materials because it destroys or at least compromises the integrity of the dielectric layer or layers during the seed deposition.
There are conventional methods for addressing the problem of overhang. Iacoponi et al. (U.S. Pat. No. 6,228,754) describe a method in which the step coverage of a seed layer is improved by removing a portion of the seed around the feature opening using a sputter etch. This method only addresses removal of excess material at the top portion of the features. Improved step coverage is achieved by adding an excess of material to all surfaces and then removing a portion of the material at the topmost region of the features. This method does not address the issue of insufficient sidewall coverage (especially in the lower regions of device features) of the seed layer due to the inability of conventional PVD to reach difficult etch topography such as etch undercuts, bowed feature profiles, microtrenches, etc. Such problematic topographies are particularly prevalent in etched low-k materials. Liu et al. describe a multi-step PVD process where in each step a portion of the seed layer is deposited. This method deposits material in each step and the final deposition profile is superposition of each of the individual profiles for each step, however, there is no re-sputter involved. This is a multi-step method, having three or more steps, making it problematic for use in a high throughput production setting.
FIG. 1H shows the completed structure of the dual Damascene process, in which copper conductive routes 125 are inlayed into the via and trench features over the seed (not depicted). Excess copper fill and portions of diffusion barrier 123 on the field have been removed (via CMP or other acceptable method) to provide a field with exposed copper inlay 125. With the advent of advanced low-k materials and increasing smaller device features, structures such as depicted in FIG. 1H, with void-free inlay 125, are harder to achieve due to issues as described above. Therefore improved methods of forming seed layers with acceptable step coverage, minimal overhang, and that access difficult etch topography are needed.
Again referring to FIG. 1H, copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated by only by diffusion barrier 123 which is itself somewhat conductive. Although conformal barrier layers are sufficiently conductive for conventional circuitry, with the continuing need for faster (signal propagation speed) and more reliable microchip circuitry, the resistance of conformal barrier layers made of the materials mentioned above is problematic. The resistance of such barrier layers can be from ten to one hundred times that of copper. Thus, to reduce resistance between the copper routes, a portion of the diffusion barrier may be etched away, specifically at the via bottom, in order to expose the lower copper plug. In this way, the subsequent copper inlay can be deposited directly onto the lower copper plug. Conventional methods for etching away diffusion barriers at the bottom of vias (for example, regions of barrier 123 contacting copper inlay 107 in FIG. 1F) are problematic in that they are not selective enough. That is, conventional etch methods remove barrier material from undesired areas as well, such as the comers (edges) of the via, trench, and field regions. This can destroy critical dimensions of the via and trench surfaces (faceting of the corners) and unnecessarily exposes the dielectric to plasma.
In addition, conventional etching methods do not address unlanded contact applications. As illustrated in FIG. 1F, a portion of diffusion barrier 123 located at via bottom 127 does not fully contact copper inlay 107. In this case, a portion of the barrier rests on copper inlay 107 and a portion rests on dielectric 103. A conventional barrier etch, meant to expose copper inlay 107, would expose both copper inlay 107 and dielectric 103 in region 127. In that case, more process steps would be needed to repair or replace diffusion barrier on the newly exposed region of dielectric 103, before any subsequent copper could be deposited thereon. Using conventional unselective xe2x80x9cblanketxe2x80x9d conformal deposition methods to re-protect the dielectric, one would create the same problem that existed before the etch, that is, higher resistance between copper routes due to the barrier itself.
What is therefore needed are improved methods of forming diffusion barriers on integrated circuit structures, selective methods in which the portion of the diffusion barrier at the bottom of vias is either completely or partially removed without sacrificing the integrity of the diffusion barrier in other regions. In this way, the resistance between inlayed metal conductive routes is reduced.
Also what is needed are improved methods of depositing seed layers on integrated circuit structures, selective methods that do not impart a high heat load on the wafer and that provide adequate sidewall coverage, especially with difficult fill topographies associated with low-k materials.
The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit in which the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. At least part of the first operation is performed in the same reaction chamber as the second operation. Some preferred methods of the invention are entirely done in a single process tool, without breaking vacuum. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In some aspects of the invention, selective etching is also used to remove contaminants under the barrier material, thus obviating a separate preclean operation.
The invention accomplishes simultaneous etch and deposition by creation of unique plasma producing process conditions such that barrier material is etched away in some regions while in other regions barrier material is deposited. Thus, the descriptive term xe2x80x9cetch to deposition ratioxe2x80x9d or xe2x80x9cE/Dxe2x80x9d is used from herein. More specifically, in the context of a partially fabricated integrated circuit having via and trench surface features, methods described herein provide that E/D varies as a function of the elevation profile of the surface features to which the plasma is applied. Generally, E/D is greatest at the bottom most regions of the wafer surface features and decreases in magnitude as elevation increases.
In this invention, there are three E/D scenarios created by control of process conditions. In the first scenario, E/D is greater than 1 at the via bottom, on the trench step, and on the field region. In the second scenario, E/D is greater than 1 at the via bottom and on the trench step, but less than one on the field region. In the third scenario, E/D is greater than 1 at the via bottom, but less than 1 on the trench step and on the field region. By using these three E/D scenarios, a variety of stack barrier layer structures are realized.
A preferred material for this etch/deposition sputter is tantalum, although the invention is not limited to tantalum. Other materials for which the invention is applicable include but are not limited to titanium, tungsten, cobalt, solid solutions (interstitial forms) of tantalum and nitrogen, and binary nitrides (e.g. TaNx, TiN, WNx). After diffusion barriers of the invention are formed, a metal conductive layer is deposited thereon. Where methods of the invention create a diffusion barrier having no barrier material at the bottom of the vias, the metal conductive layer makes direct contact with exposed metal conductive routes. Thus, one aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (b) etching through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate, and (c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts an underlying metal layer only at the bottom of the plurality of vias. Preferably at least part of (a) and all of (b) are performed in the same processing chamber. Additionally, the wafer may be precleaned before (a) in some preferred methods. In some preferred embodiments, all of (a)-(c) are performed in the same processing tool.
For unlanded vias (and in some instances for fully landed vias as well), methods of the invention create a diffusion barrier having minimal barrier material at the bottom of the vias. In this case, the resistance of the barrier between the metal conductive layer and underlying metal conductive routes is minimized. Thus, another aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) precleaning the wafer substrate, (b) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (c) etching part-way through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate such that the diffusion barrier has a minimum thickness at the bottom of the plurality of vias, and (d) depositing the metal conductive layer over the surface of the wafer substrate. Preferably at least part of (b) and all of (c) are performed in the same processing chamber. In some preferred embodiments, all of (a)-(d) are performed in the same processing tool.
Preferably methods of the invention are used in Damascene processing in which the metal conductive layer and interconnects are made of copper. In some preferred methods of the invention, the metal conductive layer is a copper seed layer. Preferably seed layers of the invention are formed using PVD, but the invention is not limited in this way. As mentioned, in some methods of the invention, all aspects of a process flow for forming a diffusion barrier and depositing a metal conductive route thereon are done in the same processing tool.
Methods of the invention create diffusion barriers having stack structures. Distinct portions of each stack may be deposited (layered) using PVD, CVD, or other methods. Thus diffusion barriers of the invention may have bilayered or trilayered structures. Preferably, the portions include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. More detail of preferred arrangements for the layering of these materials, methods of depositing, and structure of the diffusion barriers formed therefrom, will be described in the detailed description below.
Methods of the invention create diffusion barriers within integrated circuitry using at least the materials described above. Therefore, another aspect of the invention pertains to an integrated circuit or a partially fabricated integrated circuit. Preferably integrated circuits or partially fabricated integrated circuits of the invention include: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches except that there is no diffusion barrier material at the bottom of the plurality of vias, and a metal conductive layer provided thereon, such that the metal conductive layer comes in direct contact with a plurality of metal conductive routes at the bottom of the plurality of vias. Particularly (but not necessarily) for unlanded vias, yet another aspect of the invention is an integrated circuit or a partially fabricated integrated circuit comprising: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches, the diffusion barrier having a thickness of between about 50 and 400 xc3x85 on the surfaces except at the bottom of the plurality of vias where there is less than about 50 xc3x85 of diffusion barrier material; and a metal conductive layer provided thereon.
Other methods of the invention create seed layers for interconnect applications. Thus another aspect of the invention is a method for depositing a metal seed layer on a wafer substrate having a plurality of recessed device features. Such methods may be characterized by the following operations: (a) depositing a first portion of the metal seed layer on the wafer substrate, wherein the first portion comprises substantially no overhang on the opening of each of the plurality of recessed device features and the first portion includes bottom coverage in each of the plurality of recessed device features that is between about 20 and 100 percent as thick as that part of the first portion of the seed layer on the field of the wafer substrate; and (b) depositing a second portion of the metal seed layer while simultaneously redistributing at least part of the first portion on the bottom of each of the plurality of recessed device features from the bottom to the corresponding sidewalls of each of the plurality of recessed features. The bottom coverage depends upon the aspect ratio of the particular recessed device feature in which the seed layer is formed. Preferably for a recessed device feature having an aspect ratio of between about 3:1 and 4:1, the bottom coverage in (a) is between about 50 and 80 percent as thick as that part of the first portion of the seed layer on the field of the wafer substrate. Preferably the metal seed layer includes copper.
Preferably, depositing a first portion of the metal seed layer on the wafer substrate is performed using a first plasma including a plurality of metal ions, the plurality of metal ions impinging on the wafer substrate substantially perpendicular to the wafer substrate work surface. That is, preferably the metal flux is highly ionized but the ions have relatively low kinetic energy (high source power used and optionally an RF bias applied) and the metal is deposited substantially uni-directionally as described so that overhang formation is minimized. Generally, the DC (source) power used to perform (a) is more than that used to perform (b).
Preferably the first plasma is produced at a pressure of between about 1 and 30 mTorr, more preferably at about 20 mTorr. Preferably the source power used to generate the first plasma is between about 15 and 50 kW, more preferably about 36 kW. Preferably the wafer substrate is held at a temperature of between about xe2x88x92100xc2x0 C. and 50xc2x0 C., more preferably about 0xc2x0 C. during seed layer formation as described above. An RF bias may be applied. Preferably an RF frequency of between about 100 kHz and 50 MHz, more preferably about 13.56 MHz is applied to the wafer substrate during deposition of the first portion of the metal seed layer on the wafer substrate. Preferably an RF power of between about 0 and 300 W is applied, more preferably about 300 W. Preferably, the ratio of the RF power to the DC (source) power is between about 0 and 20:1 W/kW, more preferably about 8:1 W/kW. By keeping the ratio of RF power to the DC (source) power in this range, re-sputter during (a) is inhibited.
In a particularly preferred embodiment, the first plasma is subjected to a first downstream magnetic field prior to impinging on the wafer, the first magnetic field having a field strength of between about 36 and 1080 amp-turn, more preferably about 180 amp-turn. Even more preferably the first plasma is subjected to a second downstream magnetic field prior to impinging on the wafer, the second magnetic field having a field strength of between about 130 and 3960 amp-turn, more preferably about 830 amp-turn.
Preferably the first portion is between about 300 xc3x85 and 1500 xc3x85 thick on the wafer substrate field and the horizontal surfaces of each of the plurality of recessed device features. Preferably the first portion is about 800 xc3x85 thick at least on the field of the wafer substrate.
Preferably, depositing a second portion of the metal seed layer while simultaneously redistributing at least part of the first portion on the bottom of each of the plurality of recessed device features from the bottom to the corresponding sidewalls of each of the plurality of recessed features is performed using a second plasma. Preferably the second plasma includes a plurality of metal atoms and a plurality of inert gas ions, the plurality of metal atoms impinging on the wafer substrate at substantially random angles and the plurality of inert gas ions impinging on the wafer substrate substantially perpendicular to the wafer substrate work surface. That is, preferably the metal atoms are deposited at random angles, while the inert gas ions re-sputter some of the first portion from the bottom of the features to the sidewalls of the features.
Preferably the second plasma is produced at a pressure of between about 1 and 30 mTorr, more preferably at about 20 mTorr. Preferably the DC source power used to generate the second plasma is between about 1 and 15 kW, more preferably about 9 kW. Preferably an RF frequency of between about 100 kHz and 50 MHz, more preferably about 13.56 MHz is applied to the wafer substrate during deposition of the second portion of the metal seed layer with simultaneous redistribution at least part of the first portion. Preferably an RF power of between about 100 and 500 W is applied, more preferably about 400 W. Preferably, the ratio of the RF power to the DC (source) power is between about 6.6:1 W/kW and 500:1 W/kW, more preferably about 45:1 W/kW. By keeping the ratio of RF power to the DC (source) power in this range, re-sputter as described for (b) is achieved.
In a particularly preferred embodiment, the second plasma is subjected to a first downstream magnetic field prior to impinging on the wafer, the first magnetic field having a field strength of between about 36 and 1080 amp-turn, more preferably about 795 amp-turn. Even more preferably the second plasma is subjected to a second downstream magnetic field prior to impinging on the wafer, the second magnetic field having a field strength of between about 130 and 3960 amp-turn, more preferably about 1580 amp-turn.
Preferably, after depositing the first portion of the metal seed layer and depositing the second portion of the metal seed layer while simultaneously redistributing at least part of the first portion as described above, the thickness of the completed metal seed layer, at the bottom of each of the plurality of recessed device features is between about 25 xc3x85 and 500 xc3x85 thick, more preferably between about 50 xc3x85 and 100 xc3x85 thick.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.